Inspecting Ethernet Waveforms using FPGA Transceivers

In this post, I walk through the design of a sampling oscilloscope built using only the transceiver eye scan functionality of a Xilinx FPGA. A sampling oscilloscope lets you see the full analog waveform coming into the transceiver. I think it is neat that, with a few tricks, you can do this with only a Xilinx GTY, which, functionally, only provides a single 1 or 0 per bit period. It’s also nice to see what these high speed serial waveforms are actually doing in the time domain at the receiver.

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Building a Networked Key-Value-Store on an FPGA

This post is about building an FPGA based networked key-value-store in the functional hardware description language Clash. I’ll describe my FPGA-tailored hashtable design, the testing framework I built for it, and its performance and resource usage.

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The Reactive Synthesis Competition

This post is about my entry in the Reactive Synthesis Competition. I wrote it several years ago, and, as of this year, it doesn’t even win its track anymore. However, I recently saw reactive synthesis mentioned in the SymbiYosys docs and got excited because that means that someone outside of academia is possibly interested in reactive synthesis. So, I thought I’d write a very high level blog post introducing reactive synthesis and my solver.

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Introducing the SDR library

In this blog post I’m going to give a demo of my sdr library. SDR stands for software defined radio. The library is mostly written in Haskell and is available on Hackage as the (imaginatively named) sdr library. I will be using it to build an FM broadcast band receiver.

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